A New Low Power Technology for Power Reduction in Srams Using Read Stability with Reduced Transistors for Future Caches
نویسنده
چکیده
In this paper we are going to propose a new SRAM bitcell for the purpose of less power consumption, read stability,less area than the existing Schmitt trigger based SRAM and other existing designs through a new design which is combined of virtual grounding with Read error reduction logic. Designs and simulations were done using DSCH and Microwind.
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